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1 ? fn7382.7 el5132, el5133 670mhz low noise amplifiers the el5132 and el5133 are ultra-low voltage noise, high speed voltage feedback amplif iers that are ideal for applications requiring low voltage noise, including communications and imaging. these devices offer extremely low power consumption for exceptional noise performance. stable at gains as low as 10, these devices offer 120ma of drive performance. not only do these devices find perfect application in high gain applications, they maintain their performance down to lower gain settings. these amplifiers are available in small package options (sot-23) as well as the industry-standard so packages. all parts are specified for operation over the -40c to +85c temperature range. pinouts el5132 (8 ld so) top view el5133 (5 ld sot-23) top view features ? 670mhz -3db bandwidth ? ultra low noise 0.9nv/ hz ? 1000v/s slew rate ? low supply current = 12ma ? single supplies from 5v to 12v ? dual supplies from 2.5v to 6v ? fast disable on the el5132 ? pb-free plus anneal available (rohs compliant) applications ? pre-amplifier ? receiver ? filter ? if and baseband amplifier ? adc drivers ? dac buffers ? instrumentation ? communications devices 1 2 3 4 8 7 6 5 - + nc in- in+ vs- ce vs+ out nc 1 2 3 5 4 - + out vs- in+ vs+ in- data sheet march 8, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2003-2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 ordering information part number part marking tape & reel package pkg. dwg. # el5132is 5132is - 8 ld so mdp0027 el5132is-t7 5132is 7? 8 ld so mdp0027 el5132is-t13 5132is 13? 8 ld so mdp0027 el5132isz (see note) 5132isz - 8 ld so (pb-free) mdp0027 el5132isz-t7 (see note) 5132isz 7? 8 ld so (pb-free) mdp0027 el5132isz-t13 (see note) 5132isz 13? 8 ld so (pb-free) mdp0027 el5133iw-t7 bcaa 7? (3k pcs) 5 ld sot-23 mdp0038 el5133iw-t7a bcaa 7? (250 pcs) 5 ld sot-23 mdp0038 EL5133IWZ-T7 (see note) bsaa 7? (3k pcs) 5 ld sot-23 (pb-free) mdp0038 EL5133IWZ-T7a (see note) bsaa 7? (250 pcs) 5 ld sot-23 (pb-free) mdp0038 note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. el5132, el5133
3 absolute maxi mum ratings (t a = +25c) thermal information supply voltage from v s + to v s - . . . . . . . . . . . . . . . . . . . . . . . 13.2v slewrate between v s + and v s - . . . . . . . . . . . . . . . . . . . . . . . . 1v/s i in -, i in +, ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . 150ma storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +125c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v s + = +5v, v s - = -5v, r l = 500 , r f = 900 , r g = 100 , t a = +25c, unless otherwise specified. parameter description conditions min typ max unit v os offset voltage -1 0.5 1 mv t c v os offset voltage temperature coefficient measured from t min to t max 0.8 v/c ib input bias current v in = 0v 8 12 20 a i os input offset current v in = 0v -1250 400 +1250 na t c i os input bias current temperature coefficient measured from t min to t max 3na/c psrr power supply rejection ratio v s + = 4.75v to 5.25v 75 87 db cmrr common mode rejection ratio v in = 3.0 v 80 100 db cmir common mode input range guaranteed by cmrr test 3 3.3 v r in input resistance common mode 2 5 m c in input capacitance 2pf i s supply current 9.2 11 13 ma avol open loop gain v out = 2.5v, r l = 1k to gnd 5 8.5 kv/v v o output voltage swing r f = 900 , r g = 100 , r l = 150 3.1 3.5 v i sc short circuit current r l = 10 70 140 ma bw -3db bandwidth r f = 225 , a v = +10, r l = 1k 670 mhz bw 0.1db bandwidth r f = 225 , a v = +10, r l = 1k 90 mhz gbwp gain bandwidth product 3000 mhz pm phase margin r l = 1k , c l = 6pf 55 sr slew rate r l = 100 , v out = 2.5v 700 1000 v/s t r , t f rise time, fall time 0.1v step 2.0 ns os overshoot 0.1v step 10 % t s 0.01% settling time 6.6 ns dg differential gain r f = 1k , r load = 150 0.01 % dp differential phase r f = 1k , r load = 150 0.01 e n input noise voltage f = 10khz 0.9 nv/ hz i n input noise current f = 10khz 3.5 pa/ hz enable (el5132 only) t en enable time 220 ns t dis disable time 175 ns v ihce ce input high voltage for power-down v s + - 1 v v ilce ce input low voltage for power-up v s + - 3 v i s-off supply current - disabled no load, ce = 4v 13 25 a i il- ce ce pin input low current ce = v s --101a i ih- ce ce pin input high current ce = v s +1425a el5132, el5133
4 typical performance curves figure 1. gain & phase vs frequency figure 2. -3db bandwidth figure 3. 0.1db bandwidth figure 4. gain vs frequency for various +a v figure 5. gain bandwidth product fig ure 6. gain bandwidth product vs supply voltages -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) -300 -240 -180 -120 -60 0 60 120 180 240 300 phase () gain phase v s = 5v a v = +10 r g = 25 r l = 500 c l = +1pf -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) -3db bw @ 700mhz -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 100k 10m 100m frequency (hz) normalized gain (db) 0.1db bw @ 30mhz -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) a v = +30 a v = +10 a v = +20 v s = 5v r g = 25 r l = 500 c l = +1pf 20 30 40 50 60 70 1.0 10.0 100.0 frequency (mhz) gain (db) gain = 40db or 100 frequency = 31.6mhz gain bw product = 31.6 x 100 v s = 5v r l = 500 = 3160mhz 1000 1500 2000 2500 3000 3500 4000 3.0 3.5 4.0 4.5 5.0 5.5 6.0 supply voltages (v) gain-bandwidth product (mhz) v s = 5v r l = 500 el5132, el5133
5 figure 7. gain vs frequency for various v s figure 8. gain vs frequency for various r load (a v = +10) figure 9. gain vs frequency for various r load (a v = +20) figure 10. gain vs frequency for various c load (a v = +10) figure 11. gain vs frequency for various c load (a v = +20) figure 12. gain vs frequency for various r f (a v = +10) typical performance curves (continued) -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) v s = 5v v s = 6 v s =4 v s = 3v v s = 2.5v a v = +10 r g = 25 r l = 500 c l = +1pf -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) r l =100 r l =150 r l =500 r l = 1k v s = 5v a v = +10 r g = 25 c l = +1pf -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) r l =100 r l =150 r l =1k v s = 5v a v = +20 r g = 25 c l = +1pf r l =500 -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) c l =3.3pf c l = 1pf v s = 5v a v = +10 r g = 25 r f = 225 r l = 500 c l =6.8pf c l = 12pf -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) c l =1pf c l = 23pf c l =39pf v s = 5v a v = +20 r g = 25 r f = 475 r l = 500 c l = 12pf -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) r f = 225 r f = 450 v s = 5v a v = +10 r l = 500 c l = +1pf r f = 900 r f = 90 el5132, el5133
6 figure 13. gain vs frequency for various r f (a v = +20) figure 14. gain vs frequency for various c in (-) (a v = +10) figure 15. gain vs frequency for various c in (a v = +20) figure 16. open loop gain and phase vs frequency figure 17. output impedance vs frequency figure 18. cmrr vs frequency typical performance curves (continued) -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) r f = 190 r f = 475 r f = 953 r f = 1.9k v s = 5v a v = +20 r l = 500 c l = +1pf -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) c in = 0pf c in = 6.8pf c in = 2.2pf c in = 3.9pf v s = 5v a v = +10 r g = 25 r l = 500 c l = +1pf -5 -4 -3 -2 -1 0 1 2 3 4 5 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) c in = 15pf c in = 22pf c in = 8.2pf v s = 5v a v = +20 r g = 25 r l = 500 c l = +1pf c in = 12pf c in = 0pf -10 0 10 20 30 40 50 60 70 80 90 1k 10k 100k 1m 10m 100m 1g frequency (hz) open loop gain (db) -300 -240 -180 -120 -60 0 60 120 180 240 300 phase () vs = 5v open loop gain open loop phase 0.01 0.10 1 10 100 10k 100k 1m 10m 100m frequency (hz) output impedance ( ) v s = 5v cmrr (db) -20 -40 -60 -80 -100 -10 -30 -50 -70 -90 1k 10k 1m 500m frequency (hz) 100k 100m 10m -110 a v = +10 v s = 5v el5132, el5133
7 figure 19. psrr vs frequency figure 20. output swing vs frequency figure 21. group delay vs frequency figure 22. input and output isolation figure 23. harmonic distortion vs frequency figure 24. total harmonic distortion vs output voltage typical performance curves (continued) psrr (db) 0 -20 -40 -60 -80 10 -10 -30 -50 -70 1k 10k 1m 500m frequency (hz) 100k 100m 10m -90 a v = +10 v s = 5v v s + v s - -5 -4 -3 -1 0 1 2 3 4 5 1m 10m 100m 1g frequency (hz) output swing gain (db) v out = 670mv p-p v out = 240mv p-p -2 v s = 5v a v = +10 r g = 25 r l = 500 c l = +1pf v out = 6.6v p-p v out = 3.8v p-p v out = 2.1v p-p -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 0 1m 10m 100m 1g frequency (hz) group delay (ns) v s = 5v a v = +10 r g = 25 r l = 500 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 100k 1m 10m 100m frequency (hz) isolation (db) input to output output to input v s = 5v a v = +20 r g = 25 chip disabled -100 -90 -80 -70 -60 -50 -40 -30 0m 5m 10m 15m 20m 25m 30m 35m 40m fundamental frequency (hz) harmonic distortion (dbc) 3rd hd thd v s = 5v a v = +10 r g = 25 r l = 500 v out = 2v p-p 2nd hd -100 -90 -80 -70 -60 -50 -40 -30 -20 012345678 output level (v p-p ) harmonic distortion (dbc) f in = 10mhz f in = 1mhz v s = 5v a v = +10 r g = 25 r l = 500 el5132, el5133
8 figure 25. enable time figure 26. disable time figure 27. equivalent input voltage noise vs frequency figure 28. equivalent input current noise vs frequency figure 29. small signal step response_rise and fall time figure 30. large signal step response_rise and fall time typical performance curves (continued) -3 -2 -1 0 1 2 3 4 5 6 -400 -200 0 200 400 600 800 1000 1200 time (ns) amplitude (v) output signal enable signal v s = 5v r l = 500 v out = 2v p-p -2 -1 0 1 2 3 4 5 6 -1000 -800 -600 -400 -200 0 200 400 600 time (ns) amplitude (v) output signal disable signal v s = 5v r l = 500 v out = 2v p-p 0.0 0.1 1.0 10.0 100.0 10 100 1k 10k 100k 1m frequency (hz) voltage noise (nv/ hz) v s = 5v 0.1 1.0 10.0 100.0 1000.0 10 100 1k 10k 100k 1m frequency (hz) current noise (pa/ hz) v s = 5v -0.4 -0.2 0.0 0.2 0.4 -40 -20 0 20 40 60 80 100 120 140 160 180 time (ns) amplitude (v) t rise = 2.12ns t fall = 2.02ns v s = 5v a v = +10 r g = 25 r l = 500 c l = +1pf v out = 500mv -2.0 -1.0 0.0 1.0 2.0 -40 -20 0 20 40 60 80 100 120 140 160 180 time (ns) amplitude (v) t rise = 2.02ns t fall = 2.05ns v s = 5v a v = +10 r g = 25 r l = 500 c l = 1pf v out = 2.0v el5132, el5133
9 figure 31. supply current vs supply voltage figure 32. slew rate vs supply voltages figure 33. package power dissipation vs ambient temperature figure 34. package power dissipation vs ambient temperature typical performance curves (continued) 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 12.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 supply voltage (v) supply current (ma) r g = 25 r l = 500 c l = +1pf 10.0 please note that the curve showed positive current. the negative current was almost the same. 300 400 500 600 700 800 900 1000 1100 1200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 supply voltages (v) slew rate (v/s) negative slew rate a v = +10 r g = 25 r l = 500 c l = +1pf v out = 4v p-p positive slew rate 909mw j a = + 1 1 0 c / w s o 8 1.4 1.2 1 0.8 0.6 0.2 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-7 high effective thermal conductivity test board 0.4 435mw ja = +230c/w sot23-5 625mw so8 1 0.9 0.8 0.6 0.4 0.1 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-3 low effective thermal conductivity test board 0.2 0.7 0.3 0.5 391mw ja = +160c/w ja = +256c/w sot23-5 el5132, el5133
10 applications information product description the el5132, el5133 is a voltage feedback operational amplifier designed for communication and imaging applications requiring very low voltage and current noise. it also features low distortion while drawing moderately low supply current and is built on intersil's proprietary high-speed complementary bipolar process. the el5132, el5133 uses a classical voltage-feedback topology which allows them to be used in a variety of applications where current-feedback amplifiers are not appropriate be cause of restrictions placed upon the feedback element used with the amplifier. gain-bandwidth product and the -3db bandwidth the el5132, el5133 has a gain-bandwidth product of 3000mhz while using only 11ma of supply current. for gains greater than 10, their closed-loop -3db bandwidth is approximately equal to the gain-bandwidth product divided by the noise gain of the circuit. for gains of 10, higher-order poles in the amplifiers' transfer function contribute to even higher closed loop bandwidths. for example, the el5132, el5133 have a -3db bandwidth of 670mhz at a gain of 10, dropping to 150mhz at a gain of 30. it is important to note that the el5132, el5133 is des igned so that this ?extra? bandwidth in low-gain application does not come at the expense of stability. as seen in the typical performance curves, the el5132, el5133 in a gain of only 10 exhibited 0.5db of peaking with a 500 load. output drive capability the el5132 and el5133 are is designed to drive a low impedance load. it can easily drive 6v p-p signal into a 500 load. this high output drive ca pability makes the el5132, el5133 an ideal choice for rf, if, and video applications. furthermore, the el5132, el51 33 is current-limited at the output, allowing it to withstand momentary short to ground. however, the power dissipati on with output-shorted cannot exceed the power dissipation capability of the package. driving cables and capacitive loads although the el5132, el5133 is designed to drive low impedance load, capacitive loads will decreases the amplifier's phase margin. as shown in the performance curves, capacitive load can result in peaking, overshoot and possible oscillation. for optimum ac pe rformance, capacitive loads should be re duced as much as possible or isolated with a series resistor between 5 to 20 . when driving coaxial cables, double termination is always recommended for reflection-free performance. when properly terminated, the capacitance of the coaxial cable will not add to the capacitive load seen by the amplifier. disable/power-down the el5132 amplifier can be disabled placing its output in a high impedance state. when disabl e, the amplifier current is reduced to 12a. the el5132 is disabled when it ce pin is pulled up to within 1v of the power supply. similarly, the amplifier is enabled by floating or pulling its ce pin to at least 3v below the positive supply. for 5v supply, this means that an el5132 amplifier will be enabled when ce is 2v or figure 35. differential gain (%) figure 36. differential phase () typical performance curves (continued) 0.2 0 010 0.1 -0.05 0.0 -0.15 -0.20 20 30 40 50 60 70 80 90 100 differential gain (%) 0.20 0 010 0.15 -0.05 0.05 -0.15 -0.20 20 30 40 50 60 70 80 90 100 differential phase () el5132, el5133
11 less, and disabled when ce is above 4v. although the logic levels are not standard ttl, this choice of logic voltages allows the el5132 to be enabled by typing ce to ground, even in 5v single supply applications. the ce pin can be driving from cmos outputs. supply voltage range and single-supply operation the el5132 and el5133 have been designed to operate with supply voltages having a span of greater than 5v and less than 12v. in practical terms, this means that they will operate on dual supplies ranging from 2.5v to 6v. with single-supply, the el5132 and el5133 will operate from 5v to 12v. to prevent internal ci rcuit latch-up, the slew rate between the negative and positve supplies must be less than 1v/s. as supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. the el5132 and el5133 have an input range which extends to within 2v of either supply. so , for example, on 5v supplies, the el5132 and el5133 have an input range which spans 3v. the output range of the el5132 and el5133 are also quite large, extending to within 2v of the supply rail. on a 5v supply, the output is theref ore capable of swinging from -3.1v to +3.1v. single-supply output range is larger because of the increased negative s wing due to the external pull- down resistor to ground. power dissipation with the wide power supply range and large output drive capability of the el5132 and el5 133, it is possible to exceed the 150c maximum junction temperatures under certain load and power-supply conditions. it is therefore important to calculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified for the el5132 and el5133 to remain in the safe operating area. these parameters are related as follows: where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ? pd max for each amplifier can be calculated as follows: where: ?t max = maximum ambient temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = supply voltage ?i max = maximum supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance power supply bypassing and printed circuit board layout as with any high frequency devices, good printed circuit board layout is essential for optimum performance. ground plane construction is highly recommended. pin lengths should be kept as short as possible. the power supply pins must be closely bypassed to reduce the risk of oscillation. the combination of a 4.7f tantalum capacitor in parallel with 0.1f ceramic capacitor has been proven to work well when placed at each supply pin. for single supply operation, where pin 4 (v s -) is connected to the ground plane, a single 4.7f tantalum capacitor in parallel with a 0.1f ceramic capacitor across pin 8 (v s +). for good ac performance, parasitic capacitance should be kept to a minimum. ground plane construction again should be used. small chip resistors are recommended to minimize series inductance. use of sockets should be avoided since they add parasitic inductance and capacitance which will result in additional peaking and overshoot. t jmax t max ja xpd maxtotal () + = (eq. 1) pd max 2*v s i smax v s ( - v outmax ) v outmax r l ---------------------------- + = (eq. 2) el5132, el5133
12 el5132, el5133 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com el5132, el5133 sot-23 package family e1 n a d e 4 3 2 1 e1 0.15 d c 2x 0.20 c 2x e b 0.20 m d c a-b b nx 6 2 3 5 seating plane 0.10 c nx 1 3 c d 0.15 a-b c 2x a2 a1 h c (l1) l 0.25 0 +3 -0 gauge plane a mdp0038 sot-23 package family symbol millimeters tolerance sot23-5 sot23-6 a 1.45 1.45 max a1 0.10 0.10 0.05 a2 1.14 1.14 0.15 b 0.40 0.40 0.05 c 0.14 0.14 0.06 d 2.90 2.90 basic e 2.80 2.80 basic e1 1.60 1.60 basic e 0.95 0.95 basic e1 1.90 1.90 basic l 0.45 0.45 0.10 l1 0.60 0.60 reference n 5 6 reference rev. f 2/07 notes: 1. plastic or metal protrusions of 0.25mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. this dimension is measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. index area - pin #1 i.d. will be located within the indicated zone (sot23-6 only). 6. sot23-5 version has no center lead (shown as a dashed line).

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